It is well known in the communication arts that a transmit (Tx) buffer is required for both wired and wireless communications systems to interface the transmit path signal to the outside environment. In many cases, the transmit buffer is required to apply a variable gain to the transmit signal in order to increase or reduce the amplitude of the output signal. One such case occurs when the transmitted signal is part of an amplitude modulated communication system and the transmit buffer itself is used to implement the amplitude modulation function. The signal to noise ratio (SNR) requirements of such Tx buffers in most systems are extremely strict, meaning that any amplitude control circuitry should contribute no more than negligible noise to the buffer output. The reverse isolation (which can also be considered gain accuracy at low gain levels) of such transmit buffers is also an important concern. In addition, the current consumption requirements for these transmit buffers is limited such that any gain control scheme cannot ‘burn’ or waste current in order to meet the power consumption budget and the strict signal to noise requirements stated above.
A prior art digitally controlled near class E power amplifier designed for the Bluetooth wireless communication standard provides a limited number of bits for amplitude control (e.g., only 3.5 bits of amplitude control) and is used for power regulation of the transmitted constant envelope RF output. The previous lowest reported power consumption for a prior art GSM transmit chain, having no power control, is 17 mW with −7 dBm output power. The design for such a system has a transmitted power efficiency of 2.7% for an output power of 0 dBm.
There exist in the prior art multiple transmit chain architectures for transforming a digitally encoded bit stream into an RF modulated waveform at a power level suitable for transmission. The transmit power level for a cellular transceiver integrated circuit (IC) is typically around 3 dBm for interfacing with external power amplifiers (PAs). This output power level, however, is not constant in amplitude-modulated standards, such as EDGE, and must be controlled with appropriate variable-gain circuitry. Typical prior art architectures, such as single-sideband upconversion, perform digital-to-analog conversion on-chip and employ a variable gain pre-power amplifier (PPA) to transmit the required signal at the desired power level. In these architectures, the overall power consumption of the transmit chain, including all the D/A and variable gain buffer components, is at least 50 mW which is a relatively high amount of power. It is desirable to be able to reduce the power consumption of the transmit chain significantly.
As more and more communication systems incorporate increasingly complex system on chip (SoC) products which, the requirements for a gain control scheme to be used in a transmit buffer become more and more stringent. In particular, the gain control scheme is required to be robust in terms of (1) process variation insensitivity, (2) ground and substrate noise rejection and (3) ease of implementation. There is thus a long felt need for a gain control scheme for a transmit buffer that (1) can accept a digital input and output an analog output without requiring a large D/A converter (2) adds negligible noise to the output of the transmit buffer, (3) has high reverse isolation and hence good gain accuracy, (4) requires little or no quiescent current and (5) is simple to implement and is robust.